As Complementary Metal-Oxide-Semiconductor (“CMOS”) technology continues scaling to smaller critical dimensions, the intrinsic variability or mismatch between transistors, increases with the smaller transistors showing a much greater mismatch than larger ones. Random variations in device characteristics between devices of a circuit, wafer, chip or lot, are uncorrelated. Random sources of variations, which cause device mismatch between neighboring devices in a circuit, can adversely affect circuit behavior even more drastically than systematic variations in circuits such as Static Random Access Memory (“SRAM”) cells and sense amplifiers.
Indeed, since systematic sources of variation equally affect neighboring devices, device mismatch between neighboring devices as a result of systematic sources is negligible as compared to device mismatch due to random sources of device characteristic variation. Thus, random variations in device characteristics (device mismatch) cause significantly more deviation especially in circuit performance of the above mentioned circuits, than systematic variations. Since random variations in device characteristics are uncorrelated, methods for characterizing or modeling such random variations are difficult and inaccurate. Providing the necessary “fixes” at the device and circuit levels so as to limit the adverse effects of such random variations on circuit performance, are expensive by way of silicon area consumed as compared to those for systematic variations.
Although device mismatch may be caused by any number of variations in device characteristics, random variations in Vt (threshold voltage) mismatch have significant impact on circuit performance for various types of MOS circuits. In MOSFET devices, for example, random variations in Vt between neighboring transistors are due primarily to fluctuations in number and position of dopant atoms, but other sources include, for example, randomness in line edge roughness of devices. Variations in Vt mismatch of MOSFETs of an SRAM cell can significantly degrade cell stability as is understood by those of ordinary skill in the art. Furthermore, Vt mismatches of transistors of a sense amplifier can adversely impact the offset voltage. In particular, because a sense amplifier senses a differential voltage applied at the gates of two neighboring sensing devices (transistors), if there is a Vt mismatch between such devices, the mismatch adds to the voltage that the sense amplifier must counter before it can amplify the desired signal. By way of further example, Vt mismatches can affect the performance of CMOS inverters, e.g., a Vt mismatch can cause variations in the trip voltage, that is, the point at which the output of the inverter switches between logic states “1” and “0”.
SRAM is heavily impacted by Vt mismatch because SRAM designs typically use the smallest possible transistors. The variability can have a significant impact on yield. Therefore, various methods and techniques such as those describe in the co-pending U.S. patent application Ser. No. 10/643,193, which is commonly herewith to International Business Machines, Inc. and is incorporated by reference in its entirety, have been designed to measure and characterize device mismatch of semiconductor transistors due to local variations in device characteristics resulting from random sources. In particular these methods measure and characterize Vt (threshold voltage) variations between neighboring MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) of SRAM (Static Random Access Memory) cells or other logic devices. However, these methods require external analog testing equipment to perform measurements on a chip. The external analog equipment is usually slower than integrated, on-chip, digital electronics, which results in a slowing down of the manufacturing process.
Therefore a need exists to measure and overcome the problems with the prior art as discussed above.